View K8D1716UBB_379758.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

K8D1716UTB / K8D1716UBB
FLASH MEMORY
Document Title 16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory Revision History
Revision No. History
0.0 Initial Draft
Draft Date
July 25, 2004
Remark
Advance
1
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory
FEATURES
* Single Voltage, 2.7V to 3.6V for Read and Write operations * Organization 1,048,576 x 16 bit (Word mode) * Fast Read Access Time : 70ns * Read While Program/Erase Operation * Dual Bank architectures Bank 1 / Bank 2 : 8Mb / 8Mb * Secode(Security Code) Block : Extra 64K Byte block * Power Consumption (typical value @5MHz) - Read Current : 14mA - Program/Erase Current : 15mA - Read While Program or Read While Erase Current : 25mA - Standby Mode/Auto Sleep Mode : 5A * WP/ACC input pin - Allows special protection of two outermost boot blocks at VIL, regardless of block protect status - Removes special protection of two outermost boot block at VIH, the two blocks return to normal block protect status - Program time at VHH : 9s/word * Erase Suspend/Resume * Unlock Bypass Program * Hardware RESET Pin * Command Register Operation * Block Group Protection / Unprotection * Supports Common Flash Memory Interface * Industrial Temperature : -40C to 85C * Endurance : 100,000 Program/Erase Cycles Minimum * Data Retention : 10 years * Package : 48 Pin TSOP1 : 12 x 20 mm / 0.5 mm Pin pitch
FLASH MEMORY
GENERAL DESCRIPTION
The K8D1716U featuring single 3.0V power supply, is a 16Mbit NOR-type Flash Memory organized as 2Mx8 or 1M x16. The memory architecture of the device is designed to divide its memory arrays into 39 blocks to be protected by the block group. This block architecture provides highly flexible erase and program capability. The K8D1716U NOR Flash consists of two banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Access times of 70ns, 80ns and 90ns are available for the device. The devices fast access times allow high speed microprocessors to operate without wait states. The device performs a program operation in units of 8 bits (Byte) or 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/erase current in the standard and industrial temperature ranges. The K8D1716U NOR Flash Memory is created by using Samsung's advanced CMOS process technology. This device is available in 48 pin TSOP1 package. The device is compatible with EPROM applications to require high-density and costeffective nonvolatile read/write storage solutions.
PIN DESCRIPTION
Pin Name A0 - A19 Pin Function Address Inputs Data Inputs / Outputs DQ15 Data Input / Output A-1 LSB Address Word / Byte Selection Chip Enable Output Enable Hardware Reset Pin Ready/Busy Output Write Enable Hardware Write Protection/Program Acceleration Power Supply Ground No Connection
PIN CONFIGURATION
A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C WE RESET N.C WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE Vss CE A0
DQ0 - DQ14 DQ15/A-1 BYTE CE OE RESET RY/BY WE WP/ACC
48-pin TSOP1 Standard Type 12mm x 20mm
Note : Please refer to the package dimension.
Vcc VSS N.C
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
Vcc Vss
Bank1 Address
X Dec
Bank1 Cell Array
Y Dec
CE OE WE BYTE RESET RY/BY WP/ACC I/O Interface & Bank Control
Bank1 Data-In/Out Bank2 Data-In/Out
Latch & Control
Y Dec
Bank2 Address
Latch & Control
X Dec
Bank2 Cell Array
A0~A19 DQ15/A-1 DQ0~DQ14 Erase Control High Voltage Gen.
Program Control
3
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
ORDERING INFORMATION
FLASH MEMORY
K 8 D 17 1 6 U T B - T I 0 7
Samsung NOR Flash Memory Device Type Dual Bank Boot Block Access Time 07 = 70 ns 08 = 80 ns 09 = 90 ns Operating Temperature Range C = Commercial Temp. (0 C to 70 C) I = Industrial Temp. (-40 C to 85 C) Package Y = 48 TSOP1 Version B = 3rd Generation Block Architecture T = Top Boot Block B = Bottom Boot Block
Bank Division 17 = 8Mbits + 8Mbits Organization x16
Operating Voltage Range 2.7V to 3.6V
Table 1. PRODUCT LINE-UP
Part No. Vcc Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) 70ns 70ns 25ns -7 -8 2.7V~3.6V 80ns 80ns 25ns 90ns 90ns 35ns -9
Table 2. K8D1716U DEVICE BANK DIVISIONS
Device Part Number K8D1716U Bank 1 Mbit 8 Mbit Block Sizes Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword Mbit 8 Mbit Bank 2 Block Sizes Sixteen 64 Kbyte/32 Kword
4
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Table 3. Top Boot Block Address (K8D1716UT)
K8D1716UT Block BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 Bank1 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 Bank2 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A17 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A16 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Block Size (KW/KB) 4/8 4/8 4/8 4/8 4/8 4/8 4/8 4/8 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64
FLASH MEMORY
Address Range Word Mode FF000H-FFFFFH FE000H-FEFFFH FD000H-FDFFFH FC000H-FCFFFH FB000H-FBFFFH FA000H-FAFFFH F9000H-F9FFFH F8000H-F8FFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH Byte Mode 1FE000H-1FFFFFH 1FC000H-1FDFFFH 1FA000H-1FBFFFH 1F8000H-1F9FFFH 1F6000H-1F7FFFH 1F4000H-1F5FFFH 1F2000H-1F3FFFH 1F0000H-1F1FFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 000000H-00FFFFH
Table 4. Secode Block Addresses for Top Boot Devices
Device K8D1716UT Block Address A19-A12 11111xxx Block Size 64/32 (X8) Address Range 1F0000H-1FFFFFH (X16) Address Range F8000H-FFFFFH
5
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Table 5. Bottom Boot Block Address (K8D1716UB)
K8D1716UT Block BA38 BA37 BA36 BA35 BA34 BA33 BA32 Bank2 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 Bank1 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A18 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A17 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 Block Size (KW/KB) 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 32 / 64 4/8 4/8 4/8 4/8 4/8 4/8 4/8 4/8
FLASH MEMORY
Address Range Word Mode F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 07000H-07FFFH 06000H-06FFFH 05000H-05FFFH 04000H-04FFFH 03000H-03FFFH 02000H-02FFFH 01000H-01FFFH 00000H-00FFFH Byte Mode 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 00E000H-00FFFFH 00C000H-00DFFFH 00A000H-00BFFFH 008000H-009FFFH 006000H-007FFFH 004000H-005FFFH 002000H-003FFFH 000000H-001FFFH
Table 6. Secode Block Addresses for Bottom Boot Devices
Device K8D1716UB Block Address A19-A12 00000xxx Block Size 64/32 (X8) Address Range 000000H-00FFFFH (X16) Address Range 00000H-07FFFH
6
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
PRODUCT INTRODUCTION
FLASH MEMORY
The K8D1716U is a 16Mbit (16,777,216 bits) NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 39 blocks (64Kbyte x 31 , 8-Kbyte x 8). Programming is done in units of 8 bits (Byte) or 16 bits (Word). All bits of data in one or multiple blocks can be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 39 memory blocks can be hardware protected by the block group. Byte/Word modes are available for read operation. These modes can be selected via BYTE pin. The device provides read access times of 70ns, 80ns and 90ns supporting high speed microprocessors to operate without any wait states. The command set of K8D1716U is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be combined wih addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8D1716U is implemented with Internal Program/ Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8D1716U has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The device requires only 14 mA as active read current and 15 mA for program/erase operations.
Table 7. Operations Table
Operation word Read byte Stand-by Output Disable Reset word Write byte Enable Block Group Protect (3) Enable Block Group Unprotect (3) Temporary Block Group Auto Select Manufacturer ID (5) Auto Select Device Code (5) L L L X L L H H H X L L L L L X H H L X X X X X L/H (4) (4) L/H L/H L Vcc 0.3V L X L L X H X H H X H X L L X X X H (4) A9 X X X VID VID A6 L H X L L A1 H H X L L A0 L L X L H A-1 X X X X X High-Z X X X X X DIN DIN DIN X Code(See
Table 9)
CE L
OE L
WE H
BYTE H
WP/ ACC L/H
A9 A9 A9
A6 A6 A6 X X X A6
A1 A1 A1 X X X A1
A0 A0 A0 X X X A0
DQ15/ A-1 DQ15 A-1 High-Z High-Z High-Z DIN
DQ8/ DQ14 DOUT High-Z High-Z High-Z High-Z DIN
DQ0/ DQ7 DOUT DOUT High-Z High-Z High-Z DIN
RESET H H (2) H L H H VID VID VID H H
(2) L/H L/H
X X X A9
Code(See
Table 9)
Notes : 1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care. 2. WP/ACC and RESET pin are asserted at Vcc0.3 V or Vss0.3 V in the Stand-by mode. 3. Addresses must be composed of the Block address (A12 - A19). The Block Protect and Unprotect operations may be implemented via programming equipment too. Refer to the "Block Group Protection and Unprotection". 4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks will be temporarily unprotected. 5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 9.
7
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
COMMAND DEFINITIONS
FLASH MEMORY
The K8D1716U operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 8. Note that Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Block Erase Operation is in progress.
Table 8. Command Sequences
1st Cycle Command Sequence Addr Read Data Addr Reset Data Autoselect Manufacturer ID (2,3) Autoselect Device Code (2,3) Autoselect Block Group Protect Verify (2,3) Auto Select Secode Block Factory Protect Verify (2,3) Enter Secode Block Region Exit Secode Block Region Program Data Addr Unlock Bypass Data Unlock Bypass Program Unlock Bypass Reset Chip Erase Data Addr Block Erase Data Block Erase Suspend (4, 5) Block Erase Resume CFI Query (6) Data Addr 1 Data Addr 1 Data Addr 1 98H 55H 30H AAH B0H XXXH 6 AAH XXXH 55H 80H AAH 55H 30H Addr 2 Data Addr 2 Data Addr 6 AAH 555H AAAH 55H 2AAH 555H 555H 80H AAAH AAH 555H AAAH 55H 2AAH 555H 10H BA 555H 90H AAAH 00H 2AAH 555H 555H AAAH 555H AAAH 2AAH 555H 555H AAAH A0H XXXH PD XXXH 3 AAH XXXH 55H PA 20H Addr 4 Data Addr 4 Data Addr 4 Data Addr 4 Data Addr 3 Data Addr 4 Data Addr 4 AAH 555H AAAH 55H 2AAH 555H A0H 555H AAAH PD AAH 555H AAAH 55H 2AAH 555H 555H 90H AAAH 00H PA AAH 555H AAAH 55H 2AAH 555H 555H 88H AAAH XXXH AAH 555H AAAH 55H 2AAH 555H 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H 555H 1 F0H AAAH 2AAH 555H DA/ 555H DA/ AAAH 90H DA/ AAAH 90H DA/ AAAH 90H DA/ AAAH 90H AAAH DA/ X00H DA/ X00H 1 RD XXXH Cycle Word RA Byte Word Byte Word Byte Word Byte Word Byte Word Byte 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle
ECH DA/ X01H DA/ X02H
(See Table 9) BA / X02H BA/ X04H
(See Table 9) DA / X03H DA/ X06H
(See Table 9)
8
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Notes :
FLASH MEMORY
1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data DA : Dual Bank Address, BA : Block Address (A12 - A19), X = Don't care . 2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 3. The 4th cycle data of Autoselect mode is output data. The 3rd and 4th cycle bank addresses of Autoselect mode must be same. 4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode. 5. The Erase Suspend command is applicable only to the Block Erase operation. 6. Command is valid when the device is in read mode or Autoselect mode. 7. DQ8 - DQ15 are don't care in command sequence, but RD and PD is excluded. 8. A11 - A19 are also don't care, except for the case of special notice.
Table 9. K8D1716U Autoselect Codes, (High Voltage Method)
A19 to A12 DA DA A11 to A10 X X A8 to A7 X X A5 to A2 X X DQ8 to DQ15 A1 A0 BYTE =VIH X 22H BYTE =VIL X X DQ7 to DQ0 ECH A0H
Description
CE
OE
WE
A9
A6
Manufacturer ID Device Code K8D1716UT (Top Boot Block) Device Code K8D1716UB (Bottom Boot Block) Block Protection Verification
L L
L L
H H
VID VID
L L
L L
L H
L
L
H
DA
X
VID
X
L
X
L
H
22H
X
A2H 01H (Protected), 00H (Unprotected) 80H (Factory locked), 00H (Not factory locked)
L
L
H
BA
X
VID
X
L
X
H
L
X
X
Secode Block (2) Indicator Bit (DQ7)
Notes :
L
L
H
DA
X
VID
X
L
X
H
H
X
X
1. L=Logic Low=VIL, H=Logic High=VIH, DA=Dual Bank Address, BA=Block Address, X=Don't care. 2. Secode Block : Security Code Block.
9
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
DEVICE OPERATION Byte/Word Mode
FLASH MEMORY
If the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" , the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB (A-1) address pin.
Read Mode
The K8D1716U is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CE or OE is high.
Standby Mode
The K8D1716U features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is deselected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes.
Output Disable
The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state.
Automatic Sleep Mode
K8D1716U features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5A of the current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time.
tAA + 50ns
Address
Outputs
Data
Data
Data
Data
Data Auto Sleep Mode
Data
Figure 1. Auto Sleep Mode Operation
Autoselect Mode
The K8D1716U offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. In addition, this mode allows the verification of the status of write protected blocks. This mode is used by two method. The one is high voltage method to be required VID (8.5V~12.5V) on address pin A9. When A9 is held at VID and the bank address or block address is asserted, the device outputs the valid data via DQ pins(see Table 9 and Figure 2). The rest of addresses except A0, A1 and A6 are Dont Care. The other is autoselect command method that the autoselect code is accessible by the commamd sequence without VID. The manufacturer and device code may also be read via the command register. The Command Sequence is shown in Table 8 and Figure 3. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address pin, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register.
10
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
VID
FLASH MEMORY
V = VIH or VIL
A9 A6,A1,A0* DQ15-DQ0
00H 01H 22A0H or 22A2H Device Code (K8D1716U) Return to Read Mode
ECH
Manufacturer Code
Note : The addresses other than A0 , A1 and A6 are Dont care. Please refer to Table 9 for device code.
Figure 2. Autoselect Operation ( by high voltage method )
WE
A19A0(x16)/* A19A-1(x8) DQ15DQ0
555H/ AAAH
2AAH/ 555H
555H/ AAAH
00H/ 00H
01H/ 02H 22A0H or 22A2H
AAH
55H
90H
ECH
F0H
Manufacturer Code
Device Code (K8D1716U)
Return to Read Mode
Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 9 for device code.
Figure 3. Autoselect Operation ( by command sequence method )
Write (Program/Erase) Mode
The K8D1716U executes its program/erase operations by writing commands into the command register. In order to write the commands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (whichever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard microprocessor write timing.
Program
The K8D1716U can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location. WE A19A0(x16)/ A19A-1(x8) DQ15-DQ0 RY/BY
555H/ AAAH AAH
2AAH/ 555H 55H
555H/ AAAH A0H
Program Address Program Data Program Start
Figure 4. Program Command Sequence
11
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Unlock Bypass
FLASH MEMORY
The K8D1716U provides the unlock bypass mode to save its program time for program operation. The mode is invoked by the unlock bypass command sequence. Then, the unlock bypass program command sequence is required to program the device. Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode.
Chip Erase
To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
WE
A19A0(x16)/ A19A-1(x8) DQ15-DQ0
555H/ AAAH AAH
2AAH/ 555H 55H
555H/ AAAH 80H
555H AAAH AAH
2AAH/ 555H 55H
555H/ AAAH 10H Chip Erase Start
RY/BY
Figure 5. Chip Erase Command Sequence
Block Erase
To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE or CE, while the Block Erase command is latched on the rising edge of WE or CE. Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50s (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50s "time window", otherwise the Block Erase command will be ignored. The 50s "time window" is reset when the falling edge of the WE occurs within the 50s of "time window" to latch the Block Erase command. During the 50s of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50s of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase operation.
12
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
FLASH MEMORY
WE
A19A0(x16)/ A19A-1(x8) DQ15-DQ0
555H/ AAAH AAH
2AAH/ 555H 55H
555H/ AAAH 80H
555H/ AAAH AAH
2AAH/ 555H 55H
Block Address 30H Block Erase Start
RY/BY
Figure 6. Block Erase Command Sequence
Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50s. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20s to suspend the erase operation. But, when the Erase Suspend command is written during the block erase time window (50s) , the device immediately terminates the block erase time window and suspends the erase operation. After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state.
WE
A19A0(x16)/ A19A-1(x8) DQ15-DQ0
555H/ AAAH AAH
Block Address 30H
XXXH
XXXH
B0H
30H
Block Erase Command Sequence
Block Erase Start
Erase Suspend
Erase Resume
Figure 7. Erase Suspend/Resume Command Sequence
13
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Read While Write
FLASH MEMORY
The K8D1716U provides dual bank memory architecture that divides the memory array into two banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with dual bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-SuspendProgram operation. The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation.
Block Group Protection & Unprotection
The K8D1716U feature hardware block group protection. This feature will disable both program and erase operations in any combination of twenty five block groups of memory. Please refer to Tables 10 and 11. The block group protection feature is enabled using programming equipment at the user's site. The device is shipped with all block groups unprotected. This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect operation is executing. The block group protection and unprotection can be implemented by two methods. The first method needs the following conditions.
Operation Block Group Protect Block Group Unprotect
CE L L
OE H H
WE L L
BYTE X X
A9 X X
A6 L H
A1 H H
A0 L L
DQ15/ A-1 X X
DQ8/ DQ14 X X
DQ0/ DQ7 DIN DIN
RESET VID VID
Address must be inputted to the block group address (A12~A19) during block group protection operation. Please refer to Figure 9 (Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operations. The second method needs the following conditions in order to keep backward compatibility. Please refer to Figure 8.
Operation Block Group Protect Block Group Unprotect CE L L OE VID VID WE BYTE X X A9 VID VID A6 L H A1 H H A0 L L DQ15/ A-1 X X DQ8/ DQ14 X X DQ0/ DQ7 X X RESET H H
The K8D1716U needs the recovery time (20s) from the rising edge of WE in order to execute its program, erase and read operations.
500ns
Block Group Protect:150s Block Group Unprotect:500ms VID
500ns
A9
Don't Care
VID
Don't Care
OE
WE Address
Low
Block Group Address*
Notes : * Block Group Address is Don't Care during Block Group Unprotection.
Figure 8. Block Group Protect Sequence (The second method)
14
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
START COUNT = 1 RESET=VID Wait 1s
FLASH MEMORY
First Write Cycle=60h? Yes Yes Block Group Protection ? No No
No
Temporary Block Group Unprotect Mode
Block Protect Algorithm
Set up Block Group address Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 150s Verify Block Group Protect:Write 40H to Block Group address with A6=0, A1=1,A0=0 Read from Block Group address with A6=0, A1=1,A0=0 No COUNT =25? No
All Block Groups Protected ?
Yes
Block Unprotect Algorithm
Block Group , i= 0 Block Group Unprotect Write 60H with A6=1,A1=1 A0=0 Wait 15ms
Reset COUNT=1 Increment COUNT
Increment COUNT
Verify Block Group Unprotect:Write 40H to Block Group address with A6=1, A1=1,A0=0 Read from Block Group address with A6=1, A1=1,A0=0
No COUNT =1000? No
Set up next Block Group address
Data=01h?
Data=00h?
Yes Yes Device failed Protect another Block Group? No Remove VID from RESET Write RESET command END
Yes Yes Device failed Yes Yes Remove VID from RESET Write RESET command END Last Block Group verified ? No
Note : All blocks must be protected before unprotect operation is executing.
Figure 9. Block Group Protection & Unprotection Algorithms
15
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Table 10. Block Group Address (Top Boot Block)
Block Address Block Group A19 BGA0 0 A18 0 A17 0 A16 0 0 BGA1 0 0 0 1 1 BGA2 BGA3 BGA4 BGA5 BGA6 BGA7 0 0 0 1 1 1 1 BGA8 1 1 BGA9 BGA10 BGA11 BGA12 BGA13 BGA14 BGA15 BGA16 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X 0 1 0 1 0 1 0 1 X X X A14 X A13 X
FLASH MEMORY
Block A12 X BA0
BA1 to BA3
BA4 to BA7 BA8 to BA11 BA12 to BA15 BA16 to BA19 BA20 to BA23 BA24 to BA27
BA28 to BA30
BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38
16
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Table 11. Block Group Address (Bottom Boot Block)
Block Address Block Group A19 BGA0 BGA1 BGA2 BGA3 BGA4 BGA5 BGA6 BGA7 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 A17 0 0 0 0 0 0 0 0 A16 0 0 0 0 0 0 0 0 1 BGA8 0 0 0 1 0 BGA9 BGA10 BGA11 BGA12 BGA13 BGA14 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 X X X X X X 0 BGA15 1 1 1 0 1 BGA16 1 1 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1
FLASH MEMORY
Block A12 0 1 0 1 0 1 0 1 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7
BA8 to BA10
BA11 to BA14 BA15 to BA18 BA19 to BA22 BA23 to BA26 BA27 to BA30 BA31 to BA34
BA35 to BA37
BA38
17
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Temporary Block Group Unprotect
FLASH MEMORY
The protected blocks of the K8D1716U can be temporarily unprotected by applying high voltage (VID = 8.5V~12.5V) to the RESET pin. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When the RESET pin goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC pin is asserted at VIL , the two outermost boot blocks remain protected.
VID V = VIH or VIL
RESET CE WE
Program & Erase Operation at Protected Block
Figure 10. Temporary Block Group Unprotect Sequence
Write Protect (WP)
The WP/ACC pin has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID. The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph). When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 8K byte boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group protection/Unprotection". The write protected blocks can only be read. This is useful method to preserve an important program data. The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or the two blocks containing the highest addresses in a top-boot-congfigured device. (K8D1716UT : BA37 and BA38, K8D1716UB : BA0 and BA1) When the WP/ACC pin is asserted at VIH, the device reverts to whether the two outermost 8K byte boot blocks were last set to be protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected or unprotected using the method described in "Block Group protection/unprotection". Recommend that the WP/ACC pin must not be in the state of floating or unconnected, or the device may be led to malfunction.
Secode(Security Code) Block Region
The Secode Block feature provides a Flash memory region to be stored unique and permanent identification code, that is, Electronic Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently fixed at "0" and it is not changed. But once it is protected, there is no procedure to unprotect and modify the Secode Block. The Secode Block region is 64K bytes in length and is accessed through a new command sequence (see Table 8). After the system has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same addresses of the boot blocks (8KBx8). The K8D1716UT occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode 1F8000H to 1FFFFFH) and the K8D1716UB type occupies the address of the byte mode 000000H to 00FFFFH (word mode 000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to read mode.
18
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Accelerated Program Operation
FLASH MEMORY
Accelerated program operation reduces the program time. This is one of two functions provided by the WP/ACC pin. When the WP/ ACC pin is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the device to normal operation. Recommend that the WP/ACC pin must not be asserted at VHH except accelerated program operation, or the device may be damaged. In addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction.
Software Reset
The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the Erase Suspend state.
Hardware Reset
The K8D1716U offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns. When the RESET pin is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20s. If a hardware reset occurs during a program operation, the data at that particular location will be lost. Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory.
Power-up Protection
To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 1.8V. If Vcc < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 1.8V.
Write Pulse Glitch Protection
Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must be "0", while OE is "1".
Commom Flash Memory Interface
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the CFI mode. And then if the system writes the address shown in Table 12, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command.
19
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Table 12. Common Flash Memory Interface Code
Description Addresses (Word Mode) 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH
FLASH MEMORY
Addresses (Byte Mode) 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0027H 0036H 0000H 0000H 0004H 0000H 000AH 0000H 0005H 0000H 0004H 0000H 0015H 0002H 0000H 0000H 0000H 0002H 0007H 0000H 0020H 0000H 0007H 0000H 0020H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp Min. voltage(00H = no Vpp pin present) Vpp Max. voltage(00H = no Vpp pin present) Typical timeout per single byte/word write 2 us Typical timeout for Min. size buffer write 2N us(00H = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms(00H = not supported) Max. timeout for byte/word write 2 times typical Max. timeout for buffer write 2 times typical Max. timeout per individual block erase 2 times typical Max. timeout for full chip erase 2 times typical(00H = not supported) Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device
N N N N N
Erase Block Region 1 Information
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
20
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Table 12. Common Flash Memory Interface Code
Description Addresses (Word Mode) 40H 41H 42H 43H 44H 45H
FLASH MEMORY
Addresses (Byte Mode) 80H 82H 84H 86H 88H 8AH
Data 0050H 0052H 0049H 0031H 0032H 0000H
Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 0 = Not Supported, 1 = Number of blocks in per group Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme 04=K8D1x16U mode Simultaneous Operation (1) 00 = Not Supported, XX = Number of Blocks in Bank2 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page ACC(Acceleration) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV ACC(Acceleration) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Top/Bottom Boot Block Flag 02H = Bottom Boot Device, 03H = Top Boot Device
Note : 1. The number of blocks in Bank2 is device dependent. K8D1716U(8Mb/8Mb) = 10h (16blocks)
46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH
8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH
0002H 0001H 0001H 0004H 00XXH 0000H 0000H 0085H 0095H 000XH
21
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
DEVICE STATUS FLAGS
FLASH MEMORY
The K8D1716U has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as follows :
Table 13. Hardware Sequence Flags
Status
Programming Block Erase or Chip Erase Erase Suspend Read In Progress Erase Suspend Read Erase Suspend Program Programming Exceeded Time Limits Block Erase or Chip Erase Erase Suspend Program Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block
DQ7
DQ7 0 1 Data DQ7 DQ7 0 DQ7
DQ6
Toggle Toggle 1 Data Toggle Toggle Toggle Toggle
DQ5
0 0 0 Data 0 1 1 1
DQ3
0 1 0 Data 0 0 1 0
DQ2
1 Toggle Toggle (Note 1) Data 1 No Toggle (Note 2) No Toggle
RY/BY
0 0 1 1 0 0 0 0
Notes : 1. DQ2 will toggle when the device performs successive read operations from the erase suspended block. 2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.
DQ7 : Data Polling
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the device during the Erase operation, DQ7 will be low. If the device is placed in the Erase Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1s and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase Suspend Mode, an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an address belongs to a block that is not being erased, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
22
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
DQ3 : Block Erase Timer
FLASH MEMORY
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation from the program operation.
RY/BY : Ready/Busy
The K8D1716U has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the K8D1716U is placed in an Erase Suspend mode, the RY/ BY output will be High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase, RY/ BY is also valid after the rising edge of the sixth WE pulse. The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required for proper operation.
Rp VccF
Rp =
Ready / Busy open drain output
VccF (Max.) - VOL (Max.) IOL +
3.2V = 2.1mA + IL
IL
where IL is the sum of the input currents of all devices tied to the Ready / Busy ball.
Vss Device
23
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
FLASH MEMORY
Start
Start
DQ7 = Data ?
No
Yes
DQ6 = Toggle ?
No
Yes
No
DQ5 = 1 ?
No
DQ5 = 1 ?
Yes Yes
Yes No
DQ7 = Data ?
DQ6 = Toggle ?
No
Yes
Fail
Pass
Fail
Pass
Figure 11. Data Polling Algorithms
Figure 12. Toggle Bit Algorithms
Start
RESET=VID (Note 1) Perform Erase or Program Operations
RESET=VIH
Temporary Block Unprotect Completed (Note 2) Notes : 1. All protected block groups are unprotected. ( If WP/ACC = VIL , the two outermost boot blocks remain protected ) 2. All previously protected block groups are protected once again.
Figure 13. Temporary Block Group Unprotect Routine
24
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
ABSOLUTE MAXIMUM RATINGS
Parameter Vcc Voltage on any pin relative to VSS A9, OE , RESET WP/ACC All Other Pins Temperature Under Bias Storage Temperature Short Circuit Output Current Operating Temperature Commercial Industrial Tstg IOS TA (Commercial Temp.) TA (Industrial Temp.) Tbias VIN Symbol Vcc
FLASH MEMORY
Rating -0.5 to +4.0 -0.5 to +12.5 -0.5 to +12.5 -0.5 to +4.0 -10 to +125 -40 to +125 -65 to +150 5 0 to +70 -40 to + 85 C mA C C C V Unit
Notes : 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods <20ns. 2. Minimum DC voltage is -0.5V on A9, OE, RESET and WP/ACC pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on A9, OE, RESET pins is 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns. 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS ( Voltage reference to Vss )
Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7 0 Typ. 3.0 0 Max 3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Input Leakage Current A9,OE,RESET Input Leakage Current WP/ACC Input Leakage Current Output Leakage Current Active Read Current (1) Active Write Current (2) Read While Program Current (3) Read While Erase Current (3)
Program While Erase Suspend Current
Symbol ILI ILIT ILIW ILO ICC1 ICC2 ICC3 ICC4 ICC5 IACC ISB1 ISB2 ISB3 VIL VIH VHH
Test Conditions VIN=VSS to VCC, VCC=VCCmax VCC=VCCmax, A9,OE,RESET=12.5V VCC=VCCmax, WP/ACC=12.5V VOUT=VSS to VCC,VCC=VCCmax,OE=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH, WE=VIL CE=VIL, OE=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH
ACC Pin Vcc Pin
Min - 1.0 - 1.0 -0.5
0.7xVcc
Typ 14 3 15 25 25 15 5 15 5 5 5 -
Max + 1.0 35 35 + 1.0 20 6 30 50 50 35 10 30 18 18 18 0.8
VCC+0.3
Unit A A A A mA mA mA mA mA mA A A A V V V
5MHz 1MHz
ACC Accelerated Program Current Standby Current Standby Current During Reset Automatic Sleep Mode Input Low Level Input High Level
Voltage for WP/ACC Block Temporarily Unprotect and Program Acceleration (4)
VCC=VCCmax,CE, RESET=VCC0.3V WP/ACC= VCC 0.3V or Vss0.3V VCC=VCCmax, RESET=Vss 0.3V, WP/ACC=VCC 0.3V or Vss0.3V VIH=VCC0.3V, VIL=VSS0.3V, OE=VIL, IOL=IOH=0
VCC = 3.0V 0.3V
8.5
12.5
25
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
Parameter
Voltage for Autoselect and Block Protect (4)
FLASH MEMORY
Test Conditions Min 8.5 VCC-0.4 1.8 Typ Max 12.5 0.4 2.5 Unit V V V V
Symbol VID VOL VOH VLKO
VCC = 3.0V 0.3V IOL=100A, VCC=VCCmin IOH=-100A, Vcc = VCCmin
Output Low Level Output High Level Low Vcc Lock-out Voltage (5)
Notes : 1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz). The read current is typically 14 mA (@ VCC=3.0V , OE at VIH.) 2. ICC active during Internal Routine(program or erase) is in progress. 3. ICC active during Read while Write is in progress. 4. The high voltage ( VHH or VID ) must be used in the range of Vcc = 3.0V 0.3V 5. Not 100% tested. 6. Typical value are measured at Vcc = 3.0V,TA=25C , Not 100% tested.
CAPACITANCE(TA = 25 C, VCC = 3.3V, f = 1.0MHz)
Item Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Condition VIN=0V VOUT=0V VIN=0V Min Max 10 10 10 Unit pF pF pF
Note : Capacitance is periodically sampled and not 100% tested.
AC TEST CONDITION
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value 0V to Vcc 5ns Vcc/2 CL = 30pF
Vcc Vcc/2 0V
Input & Output Test Point
Device Vcc/2 CL
* CL= 30pF including Scope and Jig Capacitance
Input Pulse and Test Point
Output Load
AC CHARACTERISTICS Read Operations
VCC=2.7V~3.6V Parameter Symbol Min Read Cycle Time (1) Address Access Time Chip Enable Access Time Output Enable Time CE & OE Disable Time (1) Output Hold Time from Address, CE or OE (1)
Note : 1. Not 100% tested.
-7 Max 70 70 25 16 Min 80 0
-8 Max 80 80 25 16 Min 90 0
-9 Max 90 90 35 16 -
Unit
tRC tAA tCE tOE tDF tOH
70 0
ns ns ns ns ns ns
26
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
AC CHARACTERISTICS Write(Erase/Program)Operations Alternate WE Controlled Write
FLASH MEMORY
VCC=2.7V~3.6V Parameter Symbol Min Write Cycle Time (1) Address Setup Time tWC tAS tASO tAH tAHT tDS tDH tOES tOEH1 tOEH2 tCS tCH tWP tWPH Word Byte Word Byte tPGM 70 0 55 45 0 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 50 0 50 20 90 500 500 1 500 200 0 20 20 20 -7 Max Min 80 0 55 45 0 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 50 0 50 20 90 500 500 1 500 200 0 20 20 20 -8 Max Min 90 0 55 45 0 45 0 0 0 10 0 0 45 30 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 50 0 50 20 90 500 500 1 500 200 0 20 20 20 -9 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s sec s ns ns s ns ns ns s s ns ns ns ns ns Unit
Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Enable Hold Time Read (1) Toggle and Data Polling (1)
CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Programming Operation Accelerated Programming Operation Block Erase Operation (2) VCC Set Up Time Write Recovery Time from RY/BY RESET High Time Before Read RESET to Power Down Time Program/Erase Valid to RY/BY Delay VID Rising and Falling Time RESET Pulse Width RESET Low to RY/BY High RESET Setup Time for Temporary Unprotect RESET Low Setup Time RESET High to Address Valid Read Recovery Time Before Write CE High during toggling bit polling OE High during toggling bit polling
tACCPGM tBERS tVCS tRB tRH tRPD tBUSY tVID tRP tRRB tRSP tRSTS tRSTW tGHWL tCEPH tOEPH
Notes : 1. Not 100% tested. 2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.
27
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CE Controlled Writes
FLASH MEMORY
VCC=2.7V~3.6V Parameter Symbol Min Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Enable Hold Time Read (1) Toggle and Data Polling (1) tWC tAS tAH tDS tDH tOES tOEH1 tOEH2 tWS tWH tCP tCPH Word Byte Word Byte tPGM 70 0 45 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 25 -7 Max Min 80 0 45 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 25 -8 Max Min 90 0 45 45 0 0 0 10 0 0 45 30 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 30 -9 Max ns ns ns ns ns ns ns ns ns ns ns ns s s s s sec ns Unit
WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Programming Operation Accelerated Programming Operation Block Erase Operation (2) BYTE Switching Low to Output HIGH-Z
Notes : 1. Not 100% tested. 2.This does not include the preprogramming time.
tACCPGM tBERS tFLQZ
ERASE AND PROGRAM PERFORMANCE
Parameter Block Erase Time Chip Erase Time Word Programming Time Byte Programming Time Accelerated Byte/Word Program Time Chip Programming Time Erase/Program Endurance Word Mode Byte Mode Word Mode Byte Mode Limits Min 100,000 Typ 0.7 25 14 9 9 7 14 18 Max 15 330 210 210 150 42 54 Unit sec sec s s s s sec sec cycles Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Minimum 100,000 cycles guaranteed Comments Excludes 00H programming prior to erasure
Notes : 1. 25 C, VCC = 3.0V 100,000 cycles, typical pattern. 2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure.
28
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Read Operations
tRC
FLASH MEMORY
Address
tAA
Address Stable
CE
tOE tDF
OE
tOEH1
WE
tCE tOH
Outputs
HIGH-Z
Output Valid
HIGH-Z
RY/BY
HIGH
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time CE & OE Disable Time (1) Output Hold Time from Address, CE or OE OE Hold Time
Note : 1. Not 100% tested.
Symbol tRC tAA tCE tOE tDF tOH tOEH1
-7 Min 70 0 0 Max 70 70 25 16 Min 80 0 0
-8 Max 80 80 25 16 Min 90 0 0
-9 Max 90 90 35 16 -
Unit ns ns ns ns ns ns ns
29
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Hardware Reset/Read Operations
FLASH MEMORY
tRC
Address
tAA
Address Stable
CE
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Output Valid
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold Time from Address, CE or OE RESET Pulse Width RESET High Time Before Read
Symbol tRC tAA tCE tOH tRP tRH
-7 Min 70 0 500 50 Max 70 70 Min 80 0 500 50
-8 Max 80 80 Min 90 0 500 50
-9 Max 90 90 -
Unit ns ns ns ns ns ns
30
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Alternate WE Controlled Program Operations
tAS
FLASH MEMORY
Data Polling
PA tAH PA tRC
Address
555H
CE
tOES
OE
tWC tCH tWP tPGM
WE
tWPH tCS tDH A0H tDS PD tBUSY Status DOUT tRB tCE tOH tOE tDF
DATA
RY/BY
Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence.
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time OE Setup Time Write Pulse Width Write Pulse Width High Programming Operation Accelerated Programming Operation Read Cycle Time Chip Enable Access Time Output Enable Time CE & OE Disable Time Output Hold Time from Address, CE or OE Program/Erase Valide to RY/BY Delay Recovery Time from RY/BY Word Byte Word Byte
Symbol tWC tAS tAH tDS tDH tCS tCH tOES tWP tWPH tPGM
-7 Min 70 0 45 35 0 0 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 70 0 90 0 70 25 16 80 0 90 0 Max Min 80 0 45 35 0 0 0 0 35 25
-8 Max Min 90 0 45 45 0 0 0 0 45 30
-9 Max -
Unit ns ns ns ns ns ns ns ns ns ns us us s s
14(typ.) 9(typ.) 9(typ.) 7(typ.) 80 25 16 -
14(typ.) 9(typ.) 9(typ.) 7(typ.) 90 0 90 0 90 35 16 -
tACCPGM tRC tCE tOE tDF tOH tBUSY tRB
ns ns ns ns ns ns ns
31
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Alternate CE Controlled Program Operations
tAS
FLASH MEMORY
Data Polling
PA tAH PA
Address
555H
WE
tOES
OE
tWC tCP tPGM
CE
tWS tDH A0H tDS
tCPH
DATA
PD
Status
DOUT
tBUSY
tRB
RY/BY
Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence.
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Programming Operation Accelerated Programming Operation Word Byte Word Byte
Symbol tWC tAS tAH tDS tDH tOES tWS tWH tCP tCPH tPGM
-7 Min 70 0 45 35 0 0 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 90 0 90 0 Max Min 80 0 45 35 0 0 0 0 35 25
-8 Max Min 90 0 45 45 0 0 0 0 45 30
-9 Max -
Unit ns ns ns ns ns ns ns ns ns ns s s s s
14(typ.) 9(typ.) 9(typ.) 7(typ.) -
14(typ.) 9(typ.) 9(typ.) 7(typ.) 90 0 -
tACCPGM tBUSY tRB
Program/Erase Valide to RY/BY Delay Recovery Time from RY/BY
ns ns
32
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Word to Byte Timing Diagram for Read Operation
CE
tCE
FLASH MEMORY
OE
BYTE
tELFL
DQ0-DQ7 DQ8-DQ14 DQ15/A-1
Data Output (DQ8-DQ14) Data Output (DQ15) tFLQZ
Data Output (DQ0-DQ7)
Address Input (A-1)
Byte to Word Timing Diagram for Read Operation
CE OE
tCE
BYTE
tELFH Data Output (DQ0-DQ7) Data Output (DQ8-DQ14) Address Input (A-1) tFHQV Data Output (DQ15)
DQ0-DQ7 DQ8-DQ14 DQ15/A-1
BYTE Timing Diagram for Write Operation
CE
The falling edge of the last WE signal
WE BYTE
tSET (tAS) tHOLD(tAH)
Parameter Chip Enable Access Time CE to BYTE Switching Low or High BYTE Switching Low to Output HIGH-Z BYTE Switching High to Output Active
Symbol tCE tELFL/tELFH tFLQZ tFHQV
-7 Min Max 70 5 25 25 Min -
-8 Max 80 5 25 25 Min -
-9 Max 90 5 30 35
Unit ns ns ns ns
33
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Chip/Block Erase Operations
FLASH MEMORY
tAS
555H for Chip Erase 2AAH
tAH
Address
555H
555H
555H
2AAH
BA
tRC
CE
tOES
OE
tWP
tWC
WE
tCS
tWPH tDH
10H for Chip Erase 55H 80H AAH 55H 30H
DATA
AAH
tDS
RY/BY
Vcc
tVCS
Note : BA : Block Address
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time CE Setup Time Write Pulse Width Write Pulse Width High Read Cycle Time VCC Set Up Time
Symbol tWC tAS tAH tDS tDH tOES tCS tWP tWPH tRC tVCS
-7 Min 70 0 45 35 0 0 0 35 25 70 50 Max Min 80 0 45 35 0 0 0 35 25 80 50
-8 Max Min 90 0 45 45 0 0 0 45 30 90 50
-9 Max -
Unit ns ns ns ns ns ns ns ns ns ns s
34
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Read While Write Operations
Read tRC Command tWC DA2 (555H) tAS tAH tAA tCE Read tRC DA1 Command tWC DA2 (PA)
FLASH MEMORY
Read tRC DA1 tAS tAHT
Read tRC DA2 (PA)
Address
DA1
CE
tOE
tCEPH
OE
tOES tWP tDF tOEH2
WE
tDH
tDS
tDF
DQ
Valid Output
Valid Input (A0H)
Valid Output
Valid Input (PD)
Valid Output
Status
Note : This is an example in the program-case of the Read While Write function. DA1 : Address of Bank1, DA2 : Address of Bank 2 PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out
Parameter Write Cycle Time Write Pulse Width Write Pulse Width High Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE Setup Time OE Hold Time CE & OE Disable Time Address Hold Time CE High during toggle bit polling
Symbol tWC tWP tWPH tAS tAH tDS tDH tRC tCE tAA tOE tOES tOEH2 tDF tAHT tCEPH
-7 Min 70 35 25 0 45 35 0 70 0 10 0 20 Max 70 70 25 16 Min 80 35 25 0 45 35 0 80 0 10 0 20
-8 Max 80 80 25 16 Min 90 45 30 0 45 45 0 90 0 10 0 20
-9 Max 90 90 35 16 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
35
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Data Polling During Internal Routine Operation
CE
tOE
FLASH MEMORY
tDF
OE
tOEH2
WE
tCE tOH
DQ7
Data In
tPGM or tBERS
DQ7
*DQ7 = Valid Data
HIGH-Z
DQ0-DQ6
Data In
Status Data
Valid Data
HIGH-Z
Note : *DQ7=Vaild Data (The device has completed the internal operation).
RY/BY Timing Diagram During Program/Erase Operation
CE
The rising edge of the last WE signal
WE
Entire progrming or erase operation
RY/BY
tBUSY
Parameter Program/Erase Valid to RY/BY Delay Chip Enable Access Time Output Enable Time CE & OE Disable Time Output Hold Time from Address, CE or OE OE Hold Time
Symbol tBUSY tCE tOE tDF tOH tOEH2
-7 Min 90 0 10 Max 70 25 16 Min 90 0 10
-8 Max 80 25 16 Min 90 0 10
-9 Max 90 35 16 -
Unit ns ns ns ns ns ns
36
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation
tAHT Address* tASO CE tOEH2 WE tOEPH OE tDH DQ6/DQ2 Data In Status Data
tOE
FLASH MEMORY
tAS
tAHT
tCEPH
Status Data
Status Data
Array Data Out
RY/BY
Note : Address for the write operation must include a bank address (A19) where the data is written.
Enter Embedded Erasing
Erase Suspend Erase Erase Suspend Read
Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read
Erase Resume Erase Erase Complete
WE
DQ6
DQ2
Toggle DQ2 and DQ6 with OE or CE
Note : DQ2 is read from the erase-suspended block.
Parameter Output Enable Access Time OE Hold Time Address Hold Time Address Setup Address Setup Time Data Hold Time CE High during toggle bit polling OE High during toggle bit polling
Symbol tOE tOEH2 tAHT tASO tAS tDH tCEPH tOEPH
-7 Min 10 0 55 0 0 20 20 Max 25 Min 10 0 55 0 0 20 20
-8 Max 25 Min 10 0 55 0 0 20 20
-9 Max 35 -
Unit ns ns ns ns ns ns ns ns
37
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS RESET Timing Diagram
RY/BY
High
FLASH MEMORY
CE or OE
tRH
RESET
tRP
tREADY Reset Timings NOT during Internal Routine tREADY
RY/BY
tRB
CE or OE
tRP
RESET
Reset Timings during Internal Routine
Power-up and RESET Timing Diagram
tRSTS
RESET Vcc
Address
DATA
tAA
Parameter RESET Pulse Width RESET Low to Valid Data (During Internal Routine) RESET Low to Valid Data (Not during Internal Routine) RESET High Time Before Read RY/BY Recovery Time RESET High to Address Valid RESET Low Set-up Time
Symbol tRP tREADY tREADY tRH tRB tRSTW tRSTS
-7 Min 500 50 0 200 500 Max 20 500 Min 500 50 0 200 500
-8 Max 20 500 Min 500 50 0 200 500
-9 Max 20 500 -
Unit ns s ns ns ns ns ns
38
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
SWITCHING WAVEFORMS Block Group Protect & Unprotect Operations
VID
FLASH MEMORY
RESET
Vss,VIL, or VIH
Vss,VIL, or VIH
BGA,A6 A1,A0
Valid Block Group Protect / Unprotect
Valid Verify 40H
Block Group Protect:150s Block Group UnProtect:15ms
Valid
DATA
60H
60H
Status*
1s CE
WE
tRB
OE
tBUSY
RY/BY
Notes : Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H BGA = Block Group Address (A12 ~ A19)
Temporary Block Group Unprotect
VID RESET Vss,VIL, or VIH Vss,VIL, or VIH
CE
WE
Program or Erase Command Sequence
tVID
tRSP
tRRB
tVID
RY/BY
39
Revision 0.0 July 2004
K8D1716UTB / K8D1716UBB
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F
FLASH MEMORY
Unit :mm/Inch
20.000.20 0.7870.008
0.008-0.001
+0.07
+0.003
0.20 -0.03
#1
#48 ( 0.25 ) 0.010 12.40 0.488 MAX
0.50 0.0197
#24
#25 1.000.05 0.0390.002 1.20 0.047MAX 0.05 0.002 MIN
0.25 0.010 TYP
0.125 -0.035
0~8'C
0.45~0.75 0.018~0.030
( 0.50 ) 0.020
40
+0.003 0.005-0.001
18.400.10 0.7240.004
+0.075
12.00 0.472
Revision 0.0 July 2004
0.10 MAX 0.004

▲Up To Search▲

Price & Availability of K8D1716UBB

	To Download K8D1716UBB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .